HACC100S10V101 Bordered Single Layer Ceramic Chip Capacitor (10pF,100V)
What is a Single-Sided Bordered (Margin) Single Layer Capacitor?
In high-density microwave hybrid integrated circuits (ICs), engineers face a common assembly challenge: during die attachment, conductive silver epoxy (such as H20E) can bleed out, creep up the sides of the chip capacitor, and bridge with the top electrode, causing a catastrophic short circuit.
The HACC100S10V101 resolves this with its Single-Sided Bordered (Margin) Design. As shown in the product image, the top surface consists of a central high-purity gold electrode (TiW-Au) surrounded by a precise, un-metallized dark ceramic border (Margin). This exposed ceramic frame acts as a physical barrier, effectively blocking any epoxy bleed-out from contacting the active top electrode, guaranteeing zero-defect bonding during automated assembly.
Material & Thin-Film Metallization Structure
The HACC100S10V101 features a premium, multi-layer thin-film metallization system to ensure long-term reliability under severe thermal and mechanical stresses:
•Top Electrode: TiW-Au (Titanium-Tungsten / Gold) with an overall gold thickness of ≥ 2.5 µm Min. This thick, high-purity gold layer is optimized for high-reliability thermosonic gold wire bonding (Au wire-bonding).
•Bottom Electrode: TiW-Pt-Au (Titanium-Tungsten / Platinum / Gold) with an overall thickness of ≥ 2.5 µm Min. The inclusion of a Platinum (Pt) barrier layer prevents silver-to-gold intermetallic migration when using silver conductive epoxies, ensuring maximum adhesion.
Dimensions
Technical Specifications (HACC100S10V101)
| Technical Parameter |
Specification Value |
Test/Environmental Conditions |
| Part Number |
HACC100S10V101 |
|
| Capacitor Style |
Single Layer Ceramic Chip(SLC) |
Single-sided bordered (Margin) type |
| Capacitance |
10 pF±10% |
Measured @ 1kHz, 1Vrms, 25°C, No DCBias |
| Rated Voltage |
100VDC |
High-voltage reliability margin |
| Operating Temp. Range |
-55°Cto +125°C |
Fully complies with Tactical-gradestandards |
| Top Metallization System |
TiW-Au (Au > 2.5 um Min) |
Solderable & Wire-bondable |
| Bottom MetallizationSystem |
TiW-Pt-Au (Au > 2.5 um Min) |
Excellent conductive epoxy compatibility |
| Frequency Capability |
Optimized for GHz Band |
Ultra-low ESR and ESL at microwave bands |
Assembly & Gold Wire Bonding Best Practices
To achieve an optimal assembly yield when integrating the HACC100S10V101 into your RF modules:
1.Conductive Epoxy Die-Attach:
•Mounting with conductive silver epoxy (e.g., H20E) is highly recommended.
•Recommended Baking/Curing Profile: Bake at 120℃ for 30 minutes to ensure robust mechanical and electrical attachment.
2.Gold Wire Bonding Wedge Margin:
•To prevent micro-cracking of the ceramic or delamination of the gold film during thermosonic wire-bonding, the bonding ball/wedge must be placed at least 25 µm away from the outer edge of the gold pad.
3.Die Placement Force:
•Keep the pick-and-place nozzle force controlled to prevent localized stress on the single-layer ceramic body.
Typical High-Frequency Microwave Applications
•5G & 6G Millimeter-Wave (mmWave) Small Cells
•Optoelectronic Transceivers (100G/400G SFP/QSFP Modules)
•GaAs, GaN & InP High-Power RF Amplifiers (Bypass & Decoupling)
•LNA (Low Noise Amplifier) DC Blocking Circuits
•Satellite Communications (Satcom) and Tactical Avionics
Product Tags:
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Bordered Single Layer Capacitor 10pF 100V Low ESR Capacitor TiW-Au Metallization Images
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